1. Field of the Invention
The present invention relates to a semiconductor device including a VFET (Vertical Field Effect Transistor).
2. Description of Related Art
A VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) is generally known as a VFET. For example, a VDMOSFET adopting a trench gate structure increasingly forms the main stream of a power MOSFET.
FIG. 3 is a schematic sectional view of a semiconductor device having a VDMOSFET adopting a trench gate structure.
This VDMOSFET includes an N+-type substrate 101. An N−-type epitaxial layer 102 is laminated on the N+-type substrate 101. A P-type region 103 is formed on the surface layer of the N−-type epitaxial layer 102. A LOCOS 104 is formed on the surface of the N−-type epitaxial layer 102 along the peripheral edge of the P-type region 103. A trench 106 is formed in the P-type region 103. The trench 106 is formed by digging down the surface of the P-type region 103 to penetrate through the P-type region 103 in the thickness direction. The inner surface of the trench 106 is covered with a gate oxide film 107. The inner side of the gate oxide film 107 is filled up with polysilicon doped with an N-type impurity of a high concentration, thereby forming a gate electrode 108 in the trench 106. In the region enclosed with the LOCOS 104, an N+-type source region 105 is formed on the surface layer of the P-type region 103. A P+-type source contact region 109 is formed in the source region 105 to penetrate through the source region 105.
An interlayer dielectric film 110 is laminated on the N−-type epitaxial layer 102. A gate wire 111 and a source wire 112 are formed on the interlayer dielectric film 110. The gate wire 111 and the source wire 112 are connected to the gate electrode 108 and the source contact region 109 respectively through contact holes formed in the interlayer dielectric film 110.
On the other hand, a drain electrode 113 is formed on the rear surface (opposite to the side formed with the N−-type epitaxial layer 102) of the N+-type substrate 101.
In the VDMOSFET having this structure, a current flows from the drain electrode 113 toward the source region 105 in the direction perpendicular (vertical direction) to the surface of the N+-type substrate 101. Therefore, the device area can be remarkably reduced as compared with an LDMOSFET (Lateral Double-diffused Metal Oxide Semiconductor Field-Effect Transistor).
When the drain electrode 113 is arranged on the rear surface of the N+-type substrate 101, however, a high voltage is applied to the entire N+-type substrate 101, whereby it is difficult to isolate the region formed with the VDMOSFET from the remaining region on the N+-type substrate 101. Therefore, it is difficult to mixedly mount the VDMOSFET shown in FIG. 3 with another type of device on the N+-type substrate 101.
Therefore, an up-drain type VDMOSFET is proposed as a VDMOSFET which can be mixedly mount d on the same substrate with another type of device.
In a semiconductor device having an up-drain type VDMOSFET, a box layer 122 made of silicon oxide is laminated on an N+-type substrate 121, as shown in FIG. 4. The box layer 122 is partially removed so that the removed region of the box layer 122 serves as a transistor forming region. An N−-type epitaxial layer 123 is laminated on the box layer 122 and the part of the N+-type substrate 121 exposed from the box layer 122.
A deep trench 124 having a depth reaching the box layer 122 from the surface of the N−-type epitaxial layer 123 is formed in the N−-type epitaxial layer 123 to enclose the transistor forming region. The deep trench 124 is filled up with polysilicon. The deep trench 124 filled up with polysilicon isolates the VDMOSFET formed on the transistor forming region.
In the transistor forming region, a P-type region 125 is formed on the surface layer of the N−-type epitaxial layer 123. A trench 128 is formed in the P-type region 125. The trench 128 is formed by digging down the surface of the P-type region 125 to penetrate through the P-type region 125 in the thickness direction. The inner surface of the trench 128 is covered with a gate oxide film 129. The inner side of the gate oxide film 129 is filled up with polysilicon doped with an N-type impurity of a high concentration, thereby forming a gate electrode 130 in the trench 128. On the surface layer of the P-type region 125, an N−-type source region 127 is formed adjacent to the lateral side of the trench 128. A P+-type source contact region 131 is formed in the source region 127 to penetrate through the source region 127.
In order to ensure a vertical current path from the N−-type epitaxial layer 123 toward a source region 127, the box layer 122 is removed from the transistor forming region, thereby allowing conduction between the N+-type substrate 121 and the N−-type epitaxial layer 123.
Since the box layer 122 is removed from the transistor forming region, when the N−-type epitaxial layer 123 is formed by epitaxial growth, however, a step corresponding to the thickness of the box layer 122 is formed between the surface of the region of the N−-type epitaxial layer 123 located in the transistor forming region and the surface of the remaining region. While the thickness of the box layer 122 must be increased in order to increase the withstand voltage of the VDMOSFET, the step formed on the surface of the N−-type epitaxial layer 123 is increased in size if the thickness of the box layer 122 is increased, a problem such as defective focusing in exposure in a lithographic process for forming a resist pattern on the N−-type epitaxial layer 123.